application note AN576/0393 pcb layout optimisation a a. bremond 1. introduction protection requirements are becoming more and more well known and are often defined by rules or standards. to satisfy these requirements, there is, in the majority of cases, a standard solution or a dedicated product. however, knowledge of the disturbances and the use of suitable protection devices are not sufficient in themselves to solve the problem. in many applications, the correct design of the pcb layout is essential for success. track b track a i v cl p device to be protected disturbance source figure 1 : classical protection location 2. influence of the protection location the circuit presented in figure 1 shows the classical approach for the protection location. here the protection device * is located close to the module to be protected. when a disturbance occurs on the track a the transil p clamps the surge at a maximum voltage v cl and thus protects the sensitive part. during this clamping action there is a current through p and also in the track a. this phenomenon induces a voltage on track b, where it is close to a. to avoid this undesirable parasitic overvoltage on track b, the circuit of figure 2 is recommended. p i track b track a v cl device to be protected disturbance source figure 2 : recommended protection location 1/3
in this case the current due to the clamping phase of p remains located in the disturbance area and the track b is not affected. to summarize, it is recommended that the protection device is located as close as possible the disturbance source. for example, all the lines coming into the board ought to be protected close to the connector. 3. influence of the pcb layout on the esd protection these days, printed circuit boards are often auto-routed by computer aided design and the track lengths are not optimized. figure 3 shows the classical non-optimized layout. when a surge occurs the protection device p acts and there is a clamping voltage v cl across it. due to the fast rise time of the esd overvoltage there is a high di/dt between the points a and b. this di/dt generates, in the parasitic inductances located between a and p and between b and p, overvoltages up to several hundred volts. so the applied voltage v across the device to be protected is the sum of the clamping voltage and the voltage across the parasitic inductance : thus the sensitive module is not protected. in the case of figure 4, the design topology is based on a 4 point circuit. when a surge occurs the transil clamps at vcl and due to the design the di/dt effects remain on the left hand side of p. therefore the voltage v seen by the sensitive device is roughly equal to v cl . these days most inputs are protected against esd (though not always effectively) and so the voltage between the lines and ground never exceeds dangerous values. however, this does not prevent the total electrical potential from increasing, possibly resulting in sparks between one point of the board and the module case. to avoid this problem we recommend a bidirectionnal transil (bzw04p37b) between the printed circuit board ground and the metallic parts of the case. disturbance source a p u b device to be protected figure 3 : non-optimized layout for esd u device to be protected p i v cl disturbance source figure 4 : optimized layout for esd printed board module case figure 5 : printer circuit board protection against esd with case n.b. : the surface mount family sod6 and sod15 are particularly suited to this kind of application. a application note 2/3
4. distributed protection the printed circuit board shown in figure 5 represents a general case. in this board the input/output lines are protected close to the connector and overvoltages are cancelled close to the disturbance sources. the other lines to be protected are the power supply wires which carry 3 kinds of disturbances : - the overvoltages resulting from mains perturbations. - the surges coming from the other boards supplied by these lines. - the disturbances generated on the board by the normal operation of the resident module, for example the di/dt due to the fast switching of a buffer. to suppress these surges we suggest a powerful transil (1.5 ke for example) close to the power supply input on the board, and some lower power devices (e.g. bzw04) distributed around the board area. 5. conclusion due to the parasitic inductance of pcb tracks, a protection device chosen purely according to disturbance standards does not assure immunity from surges. carefully designed pcb layout plus correct device selection from the sgs-thomson range is essential to guarantee adequate protection. disturbance source printed board sensitive parts input / output figure 6 : distributed protection * transil devices are used as examples throughout this document, but the same arguments are valid for trisils. information furnished is believed to be accurate and reliable. however, sgs-thomson microelectronics as sumes no responsability for the consequences of use of such information nor for any inf ringement of patents or other rights of third part ies which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of sgs-thomson microelectronics. specifications mentio ned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. sgs-thomson microelectronics products are not authorized for use as critical c omponents in life support devices or systems wit hout express written approval of sgs-thomson microelectronics. ? 1995 sgs-thomson microelectronics - printed in italy - all rights reserved. sgs-thomson microelectronics group of companies australia - brazil - france - germany - hong kong - italy - japan - korea - malaysia - malta - morocco the netherlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. a application note 3/3
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